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ds556 (v1.1) may 5, 2007 www.xilinx.com 1 product specification ? 2006, 2007 xilinx, inc. all rights reserved. all xilinx tradem arks, registered trademarks, patents, and disclaimers are as li sted at http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. features ? aec-q100 device qualification and full ppap support available in both i-grade and extended temperature q-grade ? guaranteed to meet full electrical specifications over t a = -40 c to +105 c with t j maximum = +125 c (q-grade) ? optimized for 1.8v systems ? industry?s best 0.18 micron cmos cpld - optimized architecture for effective logic synthesis - multi-voltage i/o operation ? 1.5v to 3.3v ? available in the following package option - 144-pin tqfp with 118 user i/o - pb-free only for this package ? advanced system features - fastest in system programming 1.8v isp using ieee 1532 (jtag) interface - ieee1149.1 jtag boundary scan test - optional schmitt-trigger input (per pin) - unsurpassed low power management datagate enable (dge) signal control - four separate i/o banks - realdigital 100% cmos product term generation - flexible clocking modes optional dualedge triggered registers clock divider (divide by 2,4,6,8,10,12,14,16) coolclock - global signal options with macrocell control multiple global clocks with phase selection per macrocell multiple global output enables global set/reset - advanced design security - pla architecture superior pinout retention 100% product term routability across function block - open-drain output option for wired-or and led drive - optional bus-hold, 3-state or weak pullup on selected i/o pins - optional configurable grounds on unused i/os - mixed i/o voltages compatible with 1.5v, 1.8v, 2.5v, and 3.3v logic levels - hot pluggable refer to the coolrunner?-ii automotive cpld family data sheet for architecture description. warning: programming temperature range of t a = 0 c to +70 c. description the coolrunner-ii automotive 384-macrocell device is designed for both high performance and low power applica- tions. this lends power savings to high-end communication equipment and high speed to battery operated devices. due to the low power stand-by and dynamic operation, overall system reliability is improved this device consists of twenty four function blocks inter-connected by a low power advanced interconnect matrix (aim). the aim feeds 40 true and complement inputs to each function block. the function blocks consist of a 40 by 56 p-term pla and 16 macrocells which contain numer- ous configuration bits that allow for combinational or regis- tered modes of operation. additionally, these registers can be globally reset or preset and configured as a d or t flip-flop or as a d latch. there are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. a schmitt-trigger input is available on a per input pin basis. in addition to stor- ing macrocell output states, the macrocell registers may be configured as direct input registers to store signals directly from input pins. clocking is available on a global or function block basis. three global clocks are available for all function blocks as a synchronous clock source. macrocell registers can be individually configured to power up to the zero or one state. a global set/reset control line is also available to asynchro- nously set or reset selected registers during operation. additional local clock, synchronous clock-enable, asynchro- nous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-function block basis. a dualedge flip-flop feature is also available on a per mac- rocell basis. this feature allows high performance synchro- nous operation based on lower frequency clocking to help reduce the total power consumption of the device. circuitry has also been included to divide one externally supplied global clock (gck2) by eight different selections. this yields divide by even and odd clock frequencies. the use of the clock divide (division by 2) and dualedge flip-flop gives the resultant coolclock feature. 0 xa2c384 coolrunner-ii automotive cpld ds556 (v1.1) may 5, 2007 00 product specification r
xa2c384 coolrunner-ii automotive cpld 2 www.xilinx.com ds556 (v1.1) may 5, 2007 product specification r datagate is a method to selectively disable inputs of the cpld that are not of interest during certain points in time. by mapping a signal to the datagate function, lower power can be achieved due to reduction in signal switching. another feature that eases voltage translation is i/o bank- ing. four i/o banks are available on the coolrunner-ii automotive 384 macrocell device that permit easy interfac- ing to 3.3v, 2.5v, 1.8v, and 1.5v devices. the coolrunner-ii automotive 384-macrocell cpld is i/o compatible with various i/o standards (see ta b le 1 ). this device is also 1.5v i/o compatible with the use of schmitt-trigger inputs. realdigital design technology xilinx coolrunner-ii automotive cplds are fabricated on a 0.18 micron process technology which is derived from lead- ing edge fpga product development. coolrunner-ii auto- motive cplds employ realdigital a design technique that makes use of cmos technology in both the fabrication and design methodology. realdigital design technology employs a cascade of cmos gates to implement sum of products instead of traditional sense amplifier methodology. due to this technology, xilinx coolrunner-ii automotive cplds achieve both high-performance and low power operation. supported i/o standards the coolrunner-ii automotive 384-macrocell device fea- tures lvcmos and lvttl i/o implementations. see table 1 for i/o standard voltages. the lvttl i/o standard is a general purpose eia/jedec standard for 3.3v applica- tions that use an lvttl input buffer and push-pull output buffer. the lvcmos standard is used in 3.3v, 2.5v, 1.8v applications. coolrunner-ii automotive cplds are also 1.5v i/o compatible with the use of schmitt-trigger inputs. table 1: i/o standards for xa2c384 iostandard attribute output v ccio input v ccio lvttl 3.3 3.3 lvcmos33 3.3 3.3 LVCMOS25 2.5 2.5 lvcmos18 1.8 1.8 lvcmos15 (1) 1.5 1.5 (1) lvcmos15 requires schmitt-trigger inputs. figure 1: i cc vs frequency table 2: i cc vs frequency (lvcmos 1.8v t a = 25c) (1) frequency (mhz) 0 255075100125 typical i cc (ma) 0.023 17.5 35.03 52.53 70.03 87.53 notes: 1. 16-bit up/down, resetable binary counter (one counter per function block). frequency (mhz) ds556_01_092106 i cc (ma) 0 0 50 100 100 25 75 125 50
xa2c384 coolrunner-ii automotive cpld ds556 (v1.1) may 5, 2007 www.xilinx.com 3 product specification r recommended operating conditions dc electrical characteristics (over recommended operating conditions) absolute maximum ratings (1) symbol description value units v cc supply voltage relative to ground ?0.5 to 2.0 v v ccio supply voltage for output drivers ?0.5 to 4.0 v v jtag (2) jtag input voltage limits ?0.5 to 4.0 v v ccaux jtag input supply voltage ?0.5 to 4.0 v v in (1) input voltage relative to ground ?0.5 to 4.0 v v ts (1) voltage applied to 3-state output ?0.5 to 4.0 v t stg (3) storage temperature (ambient) ?65 to +150 c t j junction temperature +125 c notes: 1. maximum dc undershoot below gnd must be limited to either 0.5v or 10 ma, whichever is easiest to achieve. during transitions, the device pins may undershoot to ?2.0v or overshoot to +4.5v, provided this over or undershoot lasts less than 10 ns and with t he forcing current being limited to 200 ma. 2. valid over commercial temperature range. 3. for soldering guidelines and thermal considerations, see the device packaging information on the xilinx website. for pb-free packages, see xapp427 . symbol parameter min max units v cc supply voltage for internal logic and input buffers industrial t a = ?40c to +85c 1.7 1.9 v q-grade t a = -40 c to +105 c t j maximum = +125 c 1.7 1.9 v v ccio supply voltage for output drivers @ 3.3v operation 3.0 3.6 v supply voltage for output drivers @ 2.5v operation 2.3 2.7 v supply voltage for output drivers @ 1.8v operation 1.7 1.9 v supply voltage for output drivers @ 1.5v operation 1.4 1.6 v v ccaux supply voltage for jtag programming 1.7 3.6 v symbol parameter test conditions typical max. units i ccsb standby current industrial v cc = 1.9v, v ccio = 3.6v 79 350 a i ccsb standby current q-grade v cc = 1.9v, v ccio = 3.6v 79 4.0 ma i cc (1) dynamic current f = 1 mhz 6.0 ma f = 50 mhz 50 ma c jtag jtag input capacitance f = 1 mhz - 10 pf c clk global clock input capacitance f = 1 mhz - 12 pf c io i/o capacitance f = 1 mhz - 10 pf i il (2) input leakage current v in = 0v or v ccio to 3.9v - +/?10 a i ih (2) i/o high-z leakage v in = 0v or v ccio to 3.9v - +/?10 a notes: 1. 16-bit up/down, resetable binary counter (one counter per function block).
xa2c384 coolrunner-ii automotive cpld 4 www.xilinx.com ds556 (v1.1) may 5, 2007 product specification r lvcmos and lvttl 3.3v dc voltage specifications lvcmos 2.5v dc voltage specifications 1. the v ih max value represents the jedec specification for LVCMOS25. the coolrunner-ii input buffer can tolerate up to 3.9v without physical damage. symbol parameter test conditions min. max. units v ccio input source voltage 3.0 3.6 v v ih high level input voltage 2 3.9 v v il low level input voltage ?0.3 0.8 v v oh high level output voltage, industrial grade i oh = ?8 ma, v ccio = 3v v ccio ? 0.4v - v i oh = ?0.1 ma, v ccio = 3v v ccio ? 0.2v - v high level output voltage, q-grade i oh = ?4 ma, v ccio = 3v v ccio ? 0.4v - v i oh = ?0.1 ma, v ccio = 3v v ccio ? 0.2v - v v ol high level output voltage, industrial grade i ol = 8 ma, v ccio = 3v - 0.4 v i ol = 0.1 ma, v ccio = 3v - 0.2 v high level output voltage, q-grade i ol = 4 ma, v ccio = 3v - 0.4 v i ol = 0.1 ma, v ccio = 3v - 0.2 v symbol parameter test conditions min. max. units v ccio input source voltage 2.3 2.7 v v ih high level input voltage 1.7 v ccio + 0.3 (1) v v il low level input voltage ?0.3 0.7 v v oh high level output voltage, industrial grade i oh = ?8 ma, v ccio = 2.3v v ccio ? 0.4v - v i oh = ?0.1 ma, v ccio = 2.3v v ccio ? 0.2v - v high level output voltage, q-grade i oh = ?4 ma, v ccio = 2.3v v ccio ? 0.4v - v i oh = ?0.1 ma, v ccio = 2.3v v ccio ? 0.2v - v v ol high level output voltage, industrial grade i ol = 8 ma, v ccio = 2.3v - 0.4 v i ol = 0.1 ma, v ccio = 2.3v - 0.2 v high level output voltage, q-grade i ol = 4 ma, v ccio = 2.3v - 0.4 v i ol = 0.1 ma, v ccio = 2.3v - 0.2 v
xa2c384 coolrunner-ii automotive cpld ds556 (v1.1) may 5, 2007 www.xilinx.com 5 product specification r lvcmos 1.8v dc voltage specifications 1. the v ih max value represents the jedec specification for lvcmos18. the coolrunner-ii input buffer can tolerate up to 3.9v without physical damage. lvcmos 1.5v dc voltage specifications (1) schmitt trigger input dc voltage specifications symbol parameter test conditions min. max. units v ccio input source voltage 1.7 1.9 v v ih high level input voltage 0.65 x v ccio v ccio + 0.3 (1) v v il low level input voltage ?0.3 0.35 x v ccio v v oh high level output voltage, industrial grade i oh = ?8 ma, v ccio = 1.7v v ccio ? 0.45 - v i oh = ?0.1 ma, v ccio = 1.7v v ccio ? 0.2 - v high level output voltage, q-grade i oh = ?4 ma, v ccio = 1.7v v ccio ? 0.45 - v i oh = ?0.1 ma, v ccio = 1.7v v ccio ? 0.2 - v v ol high level output voltage, industrial grade i ol = 8 ma, v ccio = 1.7v - 0.45 v i ol = 0.1 ma, v ccio = 1.7v - 0.2 v high level output voltage, q-grade i ol = 4 ma, v ccio = 1.7v - 0.45 v i ol = 0.1 ma, v ccio = 1.7v - 0.2 v symbol parameter test conditions min. max. units v ccio input source voltage 1.4 1.6 v v t+ input hysteresis threshold voltage 0.5 x v ccio 0.8 x v ccio v v t- 0.2 x v ccio 0.5 x v ccio v v oh high level output voltage, industrial grade i oh = ?8 ma, v ccio = 1.4v v ccio ? 0.45 - v i oh = ?0.1 ma, v ccio = 1.4v v ccio ? 0.2 - v high level output voltage, q-grade i oh = ?4 ma, v ccio = 1.4v v ccio ? 0.45 - v i oh = ?0.1 ma, v ccio = 1.4v v ccio ? 0.2 - v v ol high level output voltage, industrial grade i ol = 8 ma, v ccio = 1.4v - 0.4 v i ol = 0.1 ma, v ccio = 1.4v - 0.2 v high level output voltage, q-grade i ol = 4 ma, v ccio = 1.4v - 0.4 v i ol = 0.1 ma, v ccio = 1.4v - 0.2 v notes: 1. hysteresis used on 1.5v inputs. symbol parameter test conditions min. max. units v ccio input source voltage 1.4 3.9 v v t+ input hysteresis threshold voltage 0.5 x v ccio 0.8 x v ccio v v t- 0.2 x v ccio 0.5 x v ccio v
xa2c384 coolrunner-ii automotive cpld 6 www.xilinx.com ds556 (v1.1) may 5, 2007 product specification r ac electrical characteristics over recommended operating conditions symbol parameter -10 -11 units min. max. min. max. t pd1 propagation delay single p-term - 9.2 - 9.2 ns t pd2 propagation delay or array - 10.0 - 10.0 ns t sud direct input register set-up time 4.2 - 4.5 - ns t su1 setup time fast (single p-term) 3.3 - 3.8 - ns t su2 setup time (or array) 4.1 - 4.6 - ns t hd direct input register hold time 0.0 - 0.0 - ns t h hold time (or array or p-term) 0.0 - 0.3 - ns t co clock to output - 7.9 - 7.9 ns f toggle (1) internal toggle rate - 166 - 166 mhz f system1 (2) maximum system frequency - 125 - 118 mhz f system2 (2) maximum system frequency - 114 - 108 mhz f ext1 (3) maximum external frequency - 89 - 85 mhz f ext2 (3) maximum external frequency - 83 - 80 mhz t psud direct input register p-term clock setup time 2.5 - 2.7 - ns t psu1 p-term clock setup time (single p-term) 1.9 - 2.1 - ns t psu2 p-term clock setup time (or array) 2.7 - 2.9 - ns t phd direct input register p-term clock hold time 0.4 - 1.2 - ns t ph p-term clock hold 1.3 - 1.7 - ns t pco p-term clock to output - 9.3 - 9.3 ns t oe /t od global oe to output enable/disable - 9.2 - 9.2 ns t poe /t pod p-term oe to output enable/disable - 10.2 - 10.4 ns t moe /t mod macrocell driven oe to output enable/disable - 12.5 - 12.5 ns t pao p-term set/reset to output valid - 11.6 - 11.6 ns t ao global set/reset to output valid - 11.5 - 11.5 ns t suec register clock enable setup time 3.4 - 4.0 - ns t hec register clock enable hold time 0.0 - 0.3 - ns t cw global clock pulse width high or low 3.0 - 3.0 - ns t pcw p-term pulse width high or low 10.0 - 10.0 - ns t aprpw asynchronous preset/reset pulse width (high or low) 10.0 - 10.0 - ns t dgsu set-up before datagate latch assertion 0.0 - 0.0 - ns t dgh hold to datagate latch assertion 6.0 - 6.0 - ns t dgr datagate recovery to new data 11.0 11.0 ns t dgw datagate low pulse width 5.0 - 5.0 - ns t cdrsu cdrst setup time before falling edge gclk2 2.5 - 2.5 - ns t cdrh cdrst hold time before falling edge gclk2 0.0 - 0.2 - ns t config configuration time - 200 - 200 s notes: 1. f toggle is the maximum frequency of a t flip-flop can reliably toggle (see coolrunner-ii automotive cpld family data sheet). 2. f system1 (1/t cycle ) is the internal operating frequency for a device with 16-bit resetable binary counter through one p-term per macrocell while f system2 is through the or array (one counter per function block) 3. f ext1 (1/t su1 +t co ) is the maximum external frequency using one p-term while f ext2 is through the or array 4. typical configuration current during t config is 25 ma.
xa2c384 coolrunner-ii automotive cpld ds556 (v1.1) may 5, 2007 www.xilinx.com 7 product specification r internal timing parameters symbol parameter (1) -10 -11 units min. max. min. max. buffer delays t in input buffer delay - 3.8 - 3.8 ns t din direct data register input delay - 5.5 - 5.3 ns t gck global clock buffer delay - 3.3 - 3.3 ns t gsr global set/reset buffer delay - 4.6 - 4.6 ns t gts global 3-state buffer delay - 3.7 - 3.5 ns t out output buffer delay - 3.9 - 3.9 ns t en output buffer enable/disable delay - 5.5 - 5.7 ns p-term delays t ct control term delay - 0.9 - 0.9 ns t logi1 single p-term delay adder - 0.8 - 0.8 ns t logi2 multiple p-term delay adder - 0.8 - 0.8 ns macrocell delay t pdi input to output valid - 0.7 0.7 ns t ldi setup before clock (transparent latch) - 2.5 - 2.5 ns t sui setup before clock 2.0 - 2.5 - ns t hi hold after clock 0.0 - 0.0 - ns t ecsu enable clock setup time 2.0 - 2.6 - ns t echo enable clock hold time 0.0 - 1.7 - ns t coi clock to output valid - 0.7 - 0.7 ns t aoi set/reset to output valid - 3.0 - 3.0 ns feedback delays t f feedback delay - 4.5 - 4.5 ns t oem macrocell to global oe delay - 3.0 - 2.8 ns i/o standard time adder delays 1.5v cmos t hys15 hysteresis input adder - 4.0 - 4.0 ns t out15 output adder - 1.0 - 1.0 ns t slew15 output slew rate adder - 4.0 - 4.0 ns i/o standard time adder delays 1.8v cmos t hys18 hysteresis input adder - 4.0 - 4.0 ns t out18 output adder - 0.0 - 0.0 ns t slew output slew rate adder - 4.0 - 4.0 ns i/o standard time adder delays 2.5v cmos t in25 standard input adder - 1.0 - 1.0 ns t hys25 hysteresis input adder - 3.0 - 3.0 ns t out25 output adder - 3.0 - 3.0 ns t slew25 output slew rate adder - 4.0 - 5.6 ns
xa2c384 coolrunner-ii automotive cpld 8 www.xilinx.com ds556 (v1.1) may 5, 2007 product specification r switching characteristics switching test conditions i/o standard time adder delays 3.3v cmos/ttl t in33 standard input adder - 2.0 - 2.0 ns t hys33 hysteresis input adder - 3.0 - 3.0 ns t out33 output adder - 3.0 - 3.0 ns t slew33 output slew rate adder - 4.0 - 4.0 ns notes: 1. 1.5 ns input pin signal rise/fall. internal timing parameters (continued) symbol parameter (1) -10 -11 units min. max. min. max. figure 2: derating curve for t pd number of outputs switching 12 4 8 16 4.0 5.0 6.0 v cc = v ccio = 1.8v, 25 o c t pd2 (ns) 5.5 4.5 ds095_02_053103 figure 3: ac load circuit r 1 v cc c l r 2 device under test output type lvttl33 lvcmos33 LVCMOS25 lvcmos18 lvcmos15 r 1 268 275 188 112.5 150 r 2 235 275 188 112.5 150 c l 35 pf 35 pf 35 pf 35 pf 35 pf ds092_03_09230 2 test point notes: 1. c l includes test fixtures and probe capacitance. 2. 1.5 nsec maximum rise/fall times on inputs.
xa2c384 coolrunner-ii automotive cpld ds556 (v1.1) may 5, 2007 www.xilinx.com 9 product specification r typical i/v output curves 11 figure 4: typical i/v curves for xa2c384 vo (output volts) xc384_iv_05070 3 io (output current ma) 0 0 40 10 50 20 30 60 3.0 2.5 2.0 1.5 1.0 .5 3 .5 3.3v 1.5v 1.8v 2.5v iol pin descriptions function block macrocell tqg144 i/o bank 11-2 12-2 1(gsr) 3 143 2 141422 15-2 16-- 17-- 18-- 19-- 110-- 111-- 1121402 1131392 114-2 115-2 116-2 2(gts2) 1 2 2 22-2 2(gts3) 3 3 2 2442 2(gts0) 5 5 2 26-- 27-- 28-- 29-- 210-- 211-- 212-2 213-2 214-2 2(gts1) 15 6 2 21672 pin descriptions (continued) function block macrocell tqg144 i/o bank
xa2c384 coolrunner-ii automotive cpld 10 www.xilinx.com ds556 (v1.1) may 5, 2007 product specification r 31-2 32-2 331382 341372 351362 36-- 37-- 38-- 39-- 310-- 311-- 3121352 313-2 314-2 315-2 3161342 4192 42102 43112 44122 45-2 46-- 47-- 48-- 49-- 410-- 411-- 412-2 413-2 414-2 415-2 416-2 pin descriptions (continued) function block macrocell tqg144 i/o bank 51-2 521332 531322 54-2 55-2 56-- 57-- 58-- 59-- 510-- 511-- 512-2 5131312 514-2 5151302 5161292 61-2 6 2 13 2 63142 64152 65-2 66-- 67-- 68-- 69-- 610-- 611-- 612-2 613162 614172 615-2 616182 pin descriptions (continued) function block macrocell tqg144 i/o bank
xa2c384 coolrunner-ii automotive cpld ds556 (v1.1) may 5, 2007 www.xilinx.com 11 product specification r 7(cdrst) 1 35 1 72-1 73-1 74341 75331 76-- 77-- 78-- 79-- 710-- 711-- 7(gck1) 12 32 1 713-1 714311 7(gck0) 15 30 1 716-1 81-1 8(gck2) 2 38 1 83-1 84-1 8(dge) 5 39 1 86-- 87-- 88-- 89-- 810-- 811-- 812-1 813401 814411 815421 816431 pin descriptions (continued) function block macrocell tqg144 i/o bank 91-1 92281 93-1 94-1 95-1 96-- 97-- 98-- 99-- 910-- 911--- 912-1 913-1 914-1 915261 916251 10 1 44 1 10 2 45 1 10 3 - 1 10 4 46 1 10 5 - 1 10 6 - - 10 7 - - 10 8 - - 10 9 - - 10 10 - - 10 11 - - 10 12 - 1 10 13 - 1 10 14 48 1 10 15 49 1 10 16 50 1 pin descriptions (continued) function block macrocell tqg144 i/o bank
xa2c384 coolrunner-ii automotive cpld 12 www.xilinx.com ds556 (v1.1) may 5, 2007 product specification r 11 1 24 1 11 2 23 1 11 3 22 1 11 4 21 1 11 5 20 1 11 6 - - 11 7 - - 11 8 - - 11 9 - - 11 10 - - 11 11 - - 11 12 19 1 11 13 - 1 11 14 - 1 11 15 - 1 11 16 - 1 12 1 51 1 12 2 52 1 12 3 53 1 12 4 - 1 12 5 54 1 12 6 - - 12 7 - - 12 8 - - 12 9 - - 12 10 - - 12 11 - - 12 12 - 1 12 13 - 1 12 14 - 1 12 15 - 1 12 16 - 1 pin descriptions (continued) function block macrocell tqg144 i/o bank 13 1 - 4 13 2 - 4 13 3 112 4 13 4 113 4 13 5 - 4 13 6 - - 13 7 - - 13 8 - - 13 9 - - 13 10 - - 13 11 - - 13 12 114 4 13 13 115 4 13 14 - 4 13 15 - 4 13 16 - 4 14 1 111 4 14 2 110 4 14 3 107 4 14 4 106 4 14 5 105 4 14 6 - - 14 7 - - 14 8 - - 14 9 - - 14 10 - - 14 11 - - 14 12 - 4 14 13 104 4 14 14 - 4 14 15 - 4 14 16 - 4 pin descriptions (continued) function block macrocell tqg144 i/o bank
xa2c384 coolrunner-ii automotive cpld ds556 (v1.1) may 5, 2007 www.xilinx.com 13 product specification r 15 1 - 4 15 2 116 4 15 3 - 4 15 4 - 4 15 5 117 4 15 6 - - 15 7 - - 15 8 - - 15 9 - - 15 10 - - 15 11 - - 15 12 - 4 15 13 118 4 15 14 - 4 15 15 119 4 15 16 120 4 16 1 103 4 16 2 - 4 16 3 102 4 16 4 - 4 16 5 - 4 16 6 - - 16 7 - - 16 8 - - 16 9 - - 16 10 - - 16 11 - - 16 12 - 4 16 13 - 4 16 14 101 4 16 15 - 4 16 16 100 4 pin descriptions (continued) function block macrocell tqg144 i/o bank 17 1 - 4 17 2 121 4 17 3 - 4 17 4 - 4 17 5 - 4 17 6 - - 17 7 - - 17 8 - - 17 9 - - 17 10 - - 17 11 - - 17 12 124 4 17 13 125 4 17 14 126 4 17 15 - 4 17 16 128 4 18 1 - 4 18 2 - 4 18 3 98 4 18 4 97 4 18 5 96 4 18 6 - - 18 7 - - 18 8 - - 18 9 - - 18 10 - - 18 11 - - 18 12 95 4 18 13 94 4 18 14 - 4 18 15 - 4 18 16 - 4 pin descriptions (continued) function block macrocell tqg144 i/o bank
xa2c384 coolrunner-ii automotive cpld 14 www.xilinx.com ds556 (v1.1) may 5, 2007 product specification r 19 1 - 3 19 2 - 3 19 3 74 3 19 4 75 3 19 5 76 3 19 6 - - 19 7 - - 19 8 - - 19 9 - - 19 10 - - 19 11 - - 19 12 77 3 19 13 78 3 19 14 79 3 19 15 - 3 19 16 - 3 20 1 71 3 20 2 70 3 20 3 69 3 20 4 68 3 20 5 66 3 20 6 - - 20 7 - - 20 8 - - 20 9 - - 20 10 - - 20 11 - - 20 12 - 3 20 13 64 3 20 14 - 3 20 15 - 3 20 16 - 3 pin descriptions (continued) function block macrocell tqg144 i/o bank 21 1 80 3 21 2 - 3 21 3 81 3 21 4 - 3 21 5 - 3 21 6 - - 21 7 - - 21 8 - - 21 9 - - 21 10 - - 21 11 - - 21 12 82 3 21 13 - 3 21 14 - 3 21 15 83 3 21 16 - 3 22 1 - 3 22 2 61 3 22 3 - 3 22 4 - 3 22 5 - 3 22 6 - - 22 7 - - 22 8 - - 22 9 - - 22 10 - - 22 11 - - 22 12 60 3 22 13 - 3 22 14 59 3 22 15 - 3 22 16 - 3 pin descriptions (continued) function block macrocell tqg144 i/o bank
xa2c384 coolrunner-ii automotive cpld ds556 (v1.1) may 5, 2007 www.xilinx.com 15 product specification r 23 1 - 3 23 2 - 3 23 3 85 3 23 4 86 3 23 5 87 3 23 6 - - 23 7 - - 23 8 - - 23 9 - - 23 10 - - 23 11 - - 23 12 88 3 23 13 91 3 23 14 92 3 23 15 - 3 23 16 - 3 pin descriptions (continued) function block macrocell tqg144 i/o bank 24 1 - 3 24 2 58 3 24 3 - 3 24 4 - 3 24 5 - 3 24 6 - - 24 7 - - 24 8 - - 24 9 - - 24 10 - - 24 11 - - 24 12 57 3 24 13 - 3 24 14 56 3 24 15 - 3 24 16 - 3 notes: 1. gts = global output enable, gsr = global reset/set, gck = global clock, cdrst = clock divide reset, dge = datagate enable. 2. gck, gsr, and gts pins can also be used for general purpose i/o. pin descriptions (continued) function block macrocell tqg144 i/o bank xa2c384 jtag, power/ground, no connect pins and total user i/o pin type tqg144 tck 67 tdi 63 tdo 122 tms 65 v ccaux (jtag supply voltage) 8 power internal (v cc ) 1, 37, 84 power bank 1 i/o (v ccio1 ) 27, 55 power bank 2 i/o (v ccio2 )141 power bank 3 i/o (v ccio3 ) 73, 93 power bank 4 i/o (v ccio4 ) 109, 127 ground 29, 36, 47, 62, 72, 89, 90, 99, 108, 123, 144 no connects - total user i/o (includes dual function pins) 118
xa2c384 coolrunner-ii automotive cpld 16 www.xilinx.com ds556 (v1.1) may 5, 2007 product specification r ordering information device part marking part number pin/ball spacing ja (c/watt) jc (c/watt) package type package body dimensions i/o ind. (i) (1) hi-t (q) xa2c384-10tqg144i 0.5mm 34.1 6.5 plastic quad flat pack; pb-free 20mm x 20mm 118 i xa2c384-11tqg144q 0.5mm 34.1 6.5 plastic quad flat pack; pb-free 20mm x 20mm 118 q notes: 1. i = industrial (t a = ?40 c to +85 c); q = automotive ( t a = -40 c to +105 c with t j maximum = +125 c ).. figure 5: sample package with part marking pb- free example: xa2c384 tq g 144 i device speed grade package type pb -free number of pins -10 temperature range xa2cxxx tqg144 10i device type package speed operating range this line not related to device part number r
xa2c384 coolrunner-ii automotive cpld ds556 (v1.1) may 5, 2007 www.xilinx.com 17 product specification r coolrunner-ii automotive requirements and recommendations requirements the following requirements are for all automotive applica- tions: 1. use a monotonic, fast ramp power supply to power up coolrunner-ii . a v cc ramp time of less than 1 ms is required. 2. do not float i/o pins during device operation. floating i/o pins can increase i cc as input buffers will draw 1-2 ma per floating input. in addition, when i/o pins are floated, noise can propagate to the center of the cpld. i/o pins should be appropriately terminated with bus-hold or pull-up. unused i/os can also be configured as c gnd (programmable gnd). 3. do not drive i/o pins without v cc /v ccio powered. 4. sink current when driving leds. because all xilinx cplds have n-channel pull-down transistors on outputs, it is required that an led anode is sourced figure 6: tq144 thin quad flat pack v cc i/o (1) i/o (1) i/o i/o (1) i/o (1) i/o v aux i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o v ccio1 i/o gnd i/o (2) i/o i/o (2) i/o i/o i/o (4) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 tqg144 top view v cc i/o (2) i/o (5) i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o v ccio1 i/o i/o i/o i/o i/o i/o gnd tdi i/o tms i/o tck i/o i/o i/o i/o gnd 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 gnd i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o v ccio3 i/o i/o gnd gnd i/o i/o i/o i/o v cc i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o v ccio3 gnd i/o (3) i/o v ccio2 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o v ccio4 i/o i/o i/o gnd tdo i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o v ccio4 (1) - global output enable (2) - global clock (3) - global set/reset (4) - clock divide reset (5) - datagate enable
xa2c384 coolrunner-ii automotive cpld 18 www.xilinx.com ds556 (v1.1) may 5, 2007 product specification r through a resistor externally to v cc . consequently, this will give the brightest solution. 5. avoid pull-down resistors. always use external pull-up resistors if external termination is required. this is because the coolrunner-ii automotive cpld, which includes some i/o driving circuits beyond the input and output buffers, may have contention with external pull-down resistors, and, consequently, the i/o will not switch as expected. 6. do not drive i/os pins above the v ccio assigned to its i/o bank. a. the current flow can go into v ccio and affect a user voltage regulator. b. it can also increase undesired leakage current associated with the device. c. if done for too long, it can reduce the life of the device. 7. do not rely on the i/o states before the cpld configures. during power up, the cpld i/os may be affected by internal or external signals. 8. use a voltage regulator which can provide sufficient current during device power up. as a rule of thumb, the regulator needs to provide at least three times the peak current while powering up a cpld in order to guarantee the cpld can configure successfully. 9. ensure external jtag terminations for tms, tck, tdi, tdo should comply with the ieee 1149.1. all xilinx cplds have internal weak pull-ups on tdi, tms, and tck. 10. attach all cpld v cc and gnd pins in order to have necessary power and ground supplies around the cpld. 11. decouple all v cc and v ccio pins with capacitors of 0.01 f and 0.1 f closest to the pins for each v cc /v ccio -gnd pair. 12. configure i/os properly. coolrunner-ii automotive cplds have i/o banks; therefore, signals must be assigned to appropriate banks (lvcmos33, lvcmos18 ?) recommendations the following recommendations are for all automotive appli- cations. 1. use strict synchronous design (only one clocking event) if possible. a synchronous system is more robust than an asynchronous one. 2. include jtag stakes on the pcb. jtag stakes can be used to test the part on the pcb. they add benefit in reprogramming part on the pcb, inspecting chip internals with intest, identifying stuck pins, and inspecting programming patterns (if not secured). 3. coolrunner-ii automotive cplds work with any power sequence, but it is preferable to power the v cci (internal v cc ) before the v ccio for the applications in which any glitches from device i/os are unwanted. 4. do not disregard report file warnings. software identifies potential problems when compiling, so the report file is worth inspecting to see exactly how your design is mapped onto the logic. 5. understand the timing report. this report file provides a speed summary along with warnings. read the timing file (*.tim) carefully. analyze key signal chains to determine limits to given clock(s) based on logic analysis. 6. review fitter report equations. equations can be shown in abel-like format, or can also be displayed in verilog or vhdl formats. the fitter report also includes switch settings that are very informative of other device behaviors. 7. let design software define pinouts if possible. xilinx cpld software works best when it selects the i/o pins and manages resources for users. it can spread signals around and improve pin-locking. if users must define pins, plan resources in advance. 8. perform a post-fit simulation for all speeds to identify any possible problems (such as race conditions) that might occur when fast-speed silicon is used instead of slow-speed silicon. 9. distribute ssos (simultaneously switching outputs) evenly around the cpld to reduce switching noise. 10. terminate high speed outputs to eliminate noise caused by very fast rising/falling edges. automotive warranty disclaimer this warranty does not extend to any implementation in an application or environment that is not contained within xilinx specifications. pro ducts are not designed to be fail-safe and are not warranted for use in the deployment of ai rbags. further, products are not warranted for use in applications that affect control of the vehicle unless there is a fail-safe or redundancy feature and also a warning signal to the operator of the vehicle upon failure.
xa2c384 coolrunner-ii automotive cpld ds556 (v1.1) may 5, 2007 www.xilinx.com 19 product specification r use of products in such applications is fully at the risk of customer subject to applicable laws and regulations governing limitations on product liability. additional information additional information is available for the following coolrunner-ii topics: ? xapp784: bulletproof cpld design practices ? xapp375: timing model ? xapp376: logic engine ? xapp378: advanced features ? xapp382: i/o characteristics ? xapp389: powering coolrunner-ii ? xapp399: assigning vref pins to access these and all application notes with their associ- ated reference designs, click the following link and scroll down the page until you find the document you want: coolrunner-ii data sheets and application notes device packages revision history the following table shows the revision history for this document. date version revision 10/31/06 1.0 initial xilinx release 05/05/07 1.1 change to v ih specification for 3.3v, 2.5v and 1.8v lvcmos.

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